Freescale Semiconductor /MKV58F22 /PWM0 /SM0CAPTCTRLB

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Interpret as SM0CAPTCTRLB

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)ARMB 0 (0)ONESHOTB 0 (00)EDGB0 0 (00)EDGB1 0 (0)INP_SELB 0 (0)EDGCNTB_EN 0CFBWM 0CB0CNT 0CB1CNT

ARMB=0, ONESHOTB=0, EDGB1=00, INP_SELB=0, EDGCNTB_EN=0, EDGB0=00

Description

Capture Control B Register

Fields

ARMB

Arm B

0 (0): Input capture operation is disabled.

1 (1): Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.

ONESHOTB

One Shot Mode B

0 (0): Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.

1 (1): One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.

EDGB0

Edge B 0

0 (00): Disabled

1 (01): Capture falling edges

2 (10): Capture rising edges

3 (11): Capture any edge

EDGB1

Edge B 1

0 (00): Disabled

1 (01): Capture falling edges

2 (10): Capture rising edges

3 (11): Capture any edge

INP_SELB

Input Select B

0 (0): Raw PWM_B input signal selected as source.

1 (1): Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.

EDGCNTB_EN

Edge Counter B Enable

0 (0): Edge counter disabled and held in reset

1 (1): Edge counter enabled

CFBWM

Capture B FIFOs Water Mark

CB0CNT

Capture B0 FIFO Word Count

CB1CNT

Capture B1 FIFO Word Count

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